The present invention relates to a semiconductor integrated circuit device, and particularly to an art which can be effectively adapted to semiconductor integrated circuit devices that include semiconductor memory devices such as random access memory (hereinafter referred to as RAM), read-only memory (hereinafter referred to as ROM), and the like.
A semiconductor memory device such as a RAM or a ROM is typically constituted by an electrically conductive polycrystalline silicon layer in which word lines are formed together with gate electrodes of elements that form memory cells, in order to increase the degree of integration. The electrically conductive polycrystalline silicon layer has a sheet resistivity of as relatively high as 30 to 40 ohms/ and causes the propagation of signals to be delayed.
In order to reduce the delay of signal propagation, it has been proposed to form a metal wiring layer of a small resistivity (e.g., several milliohms/ in parallel with the wiring means, and connect them together at predetermined distance intervals.
However, the inventors of the present invention have found that the above construction gives rise to the occurrence of a problem as described below. Namely, in case the metal wiring layer is broken due to defects during the manufacturing process, resistance of the wiring layer formed on the side remote from the broken portion becomes considerably greater than that of the circuit which supplies signals to the word lines. Electrically, however, the above-mentioned circuit and a memory cell are coupled together via the electrically conductive polycrystalline silicon layer having relatively large resistivity. In other words, the memory cell is selected even when the metal wiring layer has been broken.
Therefore, breakage in the metal wiring layer in the semiconductor memory device cannot be detected by the d-c operation test according to which output signals are simply checked by supplying address signals to the semiconductor memory device.
In case the metal wiring layer has been broken, memory cells formed on the side remote from the broken portion are served with select signals via the electrically conductive polycrystalline silicon layer having relatively large resistivity. Therefore, the time for selecting such memory cells becomes longer than the time for selecting other memory cells. The above-mentioned d-c operation test is not capable of detecting a semiconductor memory device (hereinafter referred to as memory) which contains memory cells that require different times for the selection operation. Consequently, memories having low reliability are often shipped.
To sort out memories that are regarded as defective, it is necessary to perform an a-c operation test according to which output signals are examined after a predetermined period of time has passed from the supply of address signals. This results in a very cumbersome sorting operation. In other words, attention must be given sufficiently to timings for supplying signals to the memory that is to be tested and to timings for examining the signals produced by the memory. Thus, the testing procedure becomes quite cumbersome.
In particular, in the case of a memory contained in a large-scale integrated circuit device such as one-chip microcomputer, in general, it is not allowed to directly supply address signals from the external unit and to directly take out the output signals to the external unit. Accordingly, the a-c operation test must be conducted by giving attention to the delay time of a logic circuit interposed between a terminal of such a one-chip microcomputer and an address input terminal of a memory contained therein, as well as to the delay time of a logic circuit interposed between a data input/output terminal of the memory contained therein and a terminal of the one-chip microcomputer. That is, by taking at least the above-mentioned two delay times into consideration, the time is found at which output signals of the memory will be produced from the microcomputer after address signals have been input to the microcomputer. The operation test is carried out by supplying address signals to the microcomputer, and examining output signals of the microcomputer after the above-found time has passed. As described above, it is necessary to find the above-mentioned time beforehand, making the operation test even more difficult. Moreover, correct results of the test are generally not expected.